Precise Interrupt Handling After a CPU receives an interrupt request from an I/O device, when does control transfer to the interrupt service routine (ISR)?

Introduction / Context:
Interrupts enable responsive I/O by letting devices signal the CPU. Precise interrupt semantics define when and how control switches from the running program to the interrupt service routine (ISR).

Given Data / Assumptions:

• Conventional, precise interrupts as implemented by mainstream CPUs.
• The current instruction is atomic from the programmer’s perspective.
• Interrupts are maskable unless disabled.

Concept / Approach:
With precise interrupts, the CPU finishes the current instruction, saves minimal context (program counter, flags, sometimes registers), and vectors to the ISR using an interrupt vector table. This guarantees a consistent architectural state at the ISR entry point.

Step-by-Step Solution:
Step 1: Device asserts an interrupt request (IRQ).Step 2: CPU acknowledges the interrupt at an instruction boundary.Step 3: CPU pushes return state (PC/flags) to a stack or dedicated area.Step 4: CPU loads the ISR address from the vector and jumps to it.Step 5: ISR services the device, then executes a return-from-interrupt instruction to resume the preempted task.

Verification / Alternative check:
Architectures may support non-maskable interrupts (NMI) and precise exceptions; the common property is transfer at a clean boundary after completing the current instruction, not in the middle of one.

Why Other Options Are Wrong:
Option A: CPUs do not arbitrarily halt for fixed durations on interrupts.Option B: Bus control is not simply handed to the device; the CPU still orchestrates transfers.Option C: Mid-instruction preemption would break precise state guarantees.Option E: Not applicable because Option D is correct.

Common Pitfalls:

• Confusing DMA bus mastering with interrupt handling.
• Assuming interrupts always preempt instantly mid-instruction.
• Forgetting that interrupts can be masked or prioritized.

Final Answer:
The CPU completes the current instruction, then branches to the ISR.