Introduction / Context:
Understanding ADC architectures is essential in digital electronics and signal processing. Successive-Approximation Register (SAR) converters dominate many medium-speed, medium-resolution applications because of their predictable conversion times and moderate complexity.
Given Data / Assumptions:
- The question references “comparing each bit, one at a time.”
- Typical SAR operation uses a binary search through bit trials.
- Other architectures (ramp, dual-slope, tracking) follow different principles.
Concept / Approach:
A SAR ADC contains a DAC, a comparator, and a SAR logic block. The SAR sets the MSB to 1, compares the DAC output to the analog input, and decides to keep or clear the bit. It proceeds bit-by-bit down to the LSB, completing in N steps for an N-bit resolution.
Step-by-Step Solution:
Initialize with MSB = 1 and others 0.Compare DAC(MSB trial) to input; keep or clear MSB accordingly.Iterate for each subsequent bit (binary search) until LSB is decided.Return the final N-bit digital result after N comparisons.
Verification / Alternative check:
Time per conversion is roughly N comparator decisions; datasheets confirm “bit-by-bit trial” behavior.
Why Other Options Are Wrong:
single-slope ramp: Integrates a ramp until comparator toggles; not bit trials.dual-slope ramp: Integrates input, then discharges with a reference for precision; no bit-by-bit search.tracking: Uses an up/down counter to follow input changes; not a binary search per sample.
Common Pitfalls:
Confusing SAR with flash ADCs; flash compares in parallel with many comparators at once.Ignoring sample-and-hold needs for stable input during the N decisions.
Final Answer:
successive-approximation converter
Discussion & Comments