In the Intel 8085 microprocessor, which hardware interrupt input is edge triggered rather than purely level sensitive?

Introduction / Context:
The Intel 8085 microprocessor supports several hardware interrupts, each with different triggering characteristics and priority levels. Some interrupts are level sensitive, meaning they respond to a sustained logic level, while others are edge triggered, responding to a transition. Knowing which interrupt uses which triggering mechanism is important for interfacing external hardware correctly.

Given Data / Assumptions:

• The 8085 has interrupt inputs such as TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• Most of these interrupts are level sensitive.
• One of them is primarily edge triggered.

Concept / Approach:
In the 8085, RST 7.5 is an edge triggered interrupt. It responds to a rising edge on its input signal. Once the edge is detected and the interrupt is acknowledged, the internal flip flop stores the request until it is serviced or cleared. In contrast, RST 6.5, RST 5.5, and INTR are level sensitive. TRAP has a combination of edge and level sensitivity but is usually described separately as a non maskable interrupt with special behavior. Standard exam questions focus on RST 7.5 as the clearly edge triggered input.

Step-by-Step Solution:
Step 1: Recall the list of vectored interrupts on the 8085: TRAP, RST 7.5, RST 6.5, and RST 5.5.Step 2: Remember that RST 7.5 latches the interrupt request on a rising edge, which is characteristic of edge triggering.Step 3: Recognize that RST 6.5 and RST 5.5 are level sensitive and require a high level to be present until acknowledged.Step 4: Match this knowledge to the option that identifies RST 7.5 as edge triggered.

Verification / Alternative check:
Reference materials for the 8085 state that RST 7.5 is a maskable, edge triggered interrupt with a higher priority than RST 6.5 and RST 5.5. Its internal flip flop captures the rising edge, which allows short pulses to be recognized even if they do not persist. This behavior distinguishes it from level sensitive inputs, which may be missed if the signal does not remain active long enough.

Why Other Options Are Wrong:
Option A: TRAP is a non maskable interrupt with a mixture of edge and level sensitivity, but the standard answer for purely edge triggered behavior in exam questions is RST 7.5.Option C: RST 6.5 is level sensitive, not edge triggered.Option D: RST 5.5 is also level sensitive.

Common Pitfalls:
Students sometimes confuse TRAP and RST 7.5 because both have special characteristics. Another common mistake is to assume that all RST interrupts behave the same way. Carefully reading the microprocessor documentation or a reliable textbook helps separate edge triggered inputs from level sensitive ones. Remembering that the seven in RST 7.5 can remind you of the edge triggered behavior is a useful mnemonic.

Final Answer:
The correct answer is RST 7.5 interrupt input, which is edge triggered.