Sizing the control interface for an 8-to-1 multiplexer: An eight-line (8:1) multiplexer requires how many data inputs and how many select inputs to address them uniquely?

Introduction / Context:
A multiplexer (MUX) selects one of N data inputs based on a binary address applied to its select lines. Determining the required number of select pins is a straightforward application of binary addressing, yet it is a frequent source of simple design errors when scaling channel counts.

Given Data / Assumptions:

• Target device: 8:1 MUX (eight inputs, one output).
• Binary addressing: k select lines can uniquely address up to 2^k inputs.
• No additional enable line is assumed in the count of “select lines.”

Concept / Approach:
To choose among eight inputs uniquely, the address space must cover 8 states. Since 2^3 = 8, exactly three select inputs are needed. The MUX also, by definition, has eight data inputs (D0–D7). Therefore, an 8:1 multiplexer has eight data inputs and three select inputs. This mapping generalizes: an N:1 MUX needs log2(N) select lines, rounded up to the next integer when N is not a power of two.

Step-by-Step Solution:

Verification / Alternative check:
Examine common parts like the 74151: it is an 8:1 MUX with three select lines (S2 S1 S0) and one enable. The enable does not change the addressing requirement; it only gates the output, confirming the count of three select inputs for eight data inputs.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing enable/strobe pins with select pins, and miscounting required select lines by forgetting the log2(N) relationship.

Final Answer:
eight data inputs and three select inputs