What is the preset condition for a ring shift counter? all FFs set to 1 all FFs

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Question
What is the preset condition for a ring shift counter?
Options
A. all FFs set to 1
B. all FFs cleared to 0
C. a single 0, the rest 1
D. a single 1, the rest 0

Correct Answer

a single 1, the rest 0

Shift Registers problems

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1. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.
Options
A. 0000
B. 1111
C. 0111
D. 1000

2. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?
Options
A. parallel-in, parallel-out
B. parallel-in, serial-out
C. serial-in, parallel-out
D. serial-in, serial-out

3. Stepper motors have become popular in digital automation systems because ________.
Options
A. of their low cost
B. they are driven by sequential digital signals
C. they can be used to provide repetitive mechanical movement
D. they are driven by sequential digital signals and can be used to provide repetitive mechanical movement

4. How can parallel data be taken out of a shift register simultaneously?
Options
A. Use the Q output of the first FF.
B. Use the Q output of the last FF.
C. Tie all of the Q outputs together.
D. Use the Q output of each FF.

10. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.
Options
A. 1101
B. 0111
C. 0001
D. 1110

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