List I | List II | ||
---|---|---|---|
A. | shift Register | 1. | Frequency division |
B. | Counter | 2. | Addressing in memory chips |
C. | Decoder | 3. | Serial to parallel Data conversion |
List I (Operator) | List II (Description) | ||
---|---|---|---|
A. | ? : | 1. | Modulus |
B. | [ ] | 2. | Array expression |
C. | % | 3. | Conditional |
and Z(0) = while in question Z(0) = 3
⟹ = 3 ⟹ k = 2.
List I (Operator) | List II (Description) | ||
---|---|---|---|
A. | ! = | 1. | Left shift |
B. | = = | 2. | Right Shift |
C. | < < | 3. | Equal to |
D. | > > | 4. | Not equal to |
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