In the given figure the line voltage after a number of reflections will be 30 V

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Question
In the given figure the line voltage after a number of reflections will be
Options
A. 30 V
B. -30 V
C. 10 V
D. -10 V

Correct Answer

10 V

More questions

2. The number of turns in a coil is doubled. If initial time constant is T, the new time constant is
Options
A. T
B. 2T
C. 4T
D.

6. In envelope detection of an AM waveform
Options
A. One side band and full-ampiitude carrier are needed
B. Both side bands and full-amplitude carrier are needed
C. Only two side bands are needed
D. Upper side band and part of carrier are needed

7. Which of the following statement regarding link loss for a satellite is wrong?
Options
A. For fixed antenna, it is inversely proportional to f²
B. For fixed frequency, it is inversely proportional to the product of the antenna aperture areas
C. For a given satellite operating at a given frequency, it is inversely proportional to
D. Loss in down-link is negligible as compared to that in uplink

8. Assertion (A): The steady state response, of a stable, linear, time invariant system, to sinusoidal input depends on initial conditions.
Reason (R): Frequency response, in steady state, is obtained by replacing s in the transfer function by j?
Options
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct but R is wrong
D. R is correct but A is wrong

9. Assertion (A): Artificial transmission lines are frequently used in laboratories.
Reason (R): An artificial transmission line can be used to represent an actual line and can also be used as a delay circuit, as attenuator, as filter network etc.
Options
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct but R is wrong
D. A is wrong but R is correct

10. Match the following:

	List I		List II
A.	TTL	1.	Low propagation delay
B.	ECL	2.	Low power consumption
C.	MOS	3.	High packing density
D.	CMOS	4.	Saturated bipolar logic

Options
A. A-4, B-1, C-3, D-2
B. A-4, B-3, C-1, D-2
C. A-4, B-3, C-2, D-1
D. A-3, B-1, C-4, D-2

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