Discussion
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- Question
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
Options- A. the clock pulse is LOW
- B. the clock pulse is HIGH
- C. the clock pulse transitions from LOW to HIGH
- D. the clock pulse transitions from HIGH to LOW
- Correct Answer
- the clock pulse transitions from LOW to HIGH
- 1. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
Options- A. active-HIGH
- B. active-LOW Discuss
- 2. In a 555 timer, three 5 kΩ resistors provide a trigger level of ________.
Options- A. 1/4 VCC and a threshold level 1/2 VCC
- B. 1/3 VCC and a threshold level 3/4 VCC
- C. 1/3 VCC and a threshold level 2/3 VCC
- D. 1/4 VCC and a threshold level 2/3 VCC Discuss
- 3. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 kΩ and a CEXT of 0.2 µF. The pulse width (tW) is approximately ________.
Options- A. 6.9 µs
- B. 6.9 ms
- C. 69 ms
- D. 690 ms Discuss
- 4. What is the hold condition of a flip-flop?
Options- A. both S and R inputs activated
- B. no active S or R input
- C. only S is active
- D. only R is active Discuss
- 5. In VHDL, how is each instance of a component addressed?
Options- A. A name followed by a colon and the name of the library primitive
- B. A name followed by a semicolon and the component type
- C. A name followed by the library being used
- D. A name followed by the component library number Discuss
- 6. A 555 operating as a monostable multivibrator has a C1 = 0.01 µF. Determine R1 for a pulse width of 2 ms.
Options- A. 200 kΩ
- B. 182 kΩ
- C. 91 kΩ
- D. 182 Ω Discuss
- 7. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.
Options- A. 1 kHz
- B. 2 kHz
- C. 4 kHz
- D. 16 kHz Discuss
- 8. Edge-triggered flip-flops must have:
Options- A. very fast response times.
- B. at least two inputs to handle rising and falling edges.
- C. a pulse transition detector.
- D. active-LOW inputs and complemented outputs. Discuss
- 9. What is the difference between the 7476 and the 74LS76?
Options- A. the 7476 is master-slave, the 74LS76 is master-slave
- B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
- C. the 7476 is edge-triggered, the 74LS76 is master-slave
- D. the 7476 is master-slave, the 74LS76 is edge-triggered Discuss
- 10. With regard to a D latch, ________.
Options- A. the Q output follows the D input when EN is LOW
- B. the Q output is opposite the D input when EN is LOW
- C. the Q output follows the D input when EN is HIGH
- D. the Q output is HIGH regardless of EN's input state Discuss
Flip-Flops problems
Search Results
Correct Answer: active-HIGH
Correct Answer: 1/3 VCC and a threshold level 2/3 VCC
Correct Answer: 6.9 ms
Correct Answer: no active S or R input
Correct Answer: A name followed by a colon and the name of the library primitive
Correct Answer: 182 kΩ
Correct Answer: 2 kHz
Correct Answer: a pulse transition detector.
Correct Answer: the 7476 is master-slave, the 74LS76 is edge-triggered
Correct Answer: the Q output follows the D input when EN is HIGH
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