Which processor structure is pipe lined?

Correct Answer: 8085 is a one address microprocessor In 8085 interrupts are classified by software and hardware interrupts

Correct Answer: The MESI protocol is also known as illinois protocol due to its development the University of illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol MESI is the most common which supports write-back cache its use in personal computers became widespread with the introduction of intel's pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"/

Correct Answer: Because 8085 processor is 8 bit ALU (arithmetic logic review) Similarly 8086 processor has 16 bit ALU

Correct Answer: The Transmission-Gate's input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D-Latch enable inputs (EN) and the Transmission-Gate outputs is the D_LATCH output(Q)

Correct Answer: There are situations, called hazards, that prevent the next insturction in the instruction stream from executing during its designated clock cycle hazards reduce the performance from the ideal speedup gained by pipelining There are three classes of Hazards: 1 Structural hazards: It arise from resource conficts when the hardware cannot support all possible combinations of instructions simultaniously in overlapped execution 2 Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline 3control hazards it arise from the pipelining of branches and other instructions that chage the PC

Correct Answer: The processor made of PMOS / NMOS / HMOS / HCMOS technology is called 1st / 2nd / 3rd / 4th generation processor, and it is made up of 4 / 8 / 16 / 32 bits

Correct Answer: The original 8086, which only had 1 MB of memory This megabyte is split into low memory for IRQ tables, application memory and high memory

Correct Answer: Because there is no need address traansaction between processor and peripheral device but data bus is needed because data has to be read and write

Correct Answer: TST 75 is a raising edge-triggering interrupt

Correct Answer: Stack pointer and Program counter all have 16 bits