Correct Answer: There are situations, called hazards, that prevent the next insturction in the instruction stream from executing during its designated clock cycle hazards reduce the performance from the ideal speedup gained by pipelining There are three classes of Hazards: 1 Structural hazards: It arise from resource conficts when the hardware cannot support all possible combinations of instructions simultaniously in overlapped execution 2 Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline 3control hazards it arise from the pipelining of branches and other instructions that chage the PC
Correct Answer: The Transmission-Gate's input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D-Latch enable inputs (EN) and the Transmission-Gate outputs is the D_LATCH output(Q)
8. why 8085 processor, is called an 8 bit processor?
Correct Answer: The MESI protocol is also known as illinois protocol due to its development the University of illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol MESI is the most common which supports write-back cache its use in personal computers became widespread with the introduction of intel's pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"/
10. Give an example of one address microprocessor?